1. Field of the Invention
This invention relates generally to electronic integrated circuits, and more particularly to a circuit and method for programming programmable interconnect points (PIPs) in a field programmable gate array (FPGA).
2. Description of the Background Art
FIG. 1 illustrates a simplified schematic diagram of the routing matrix of a conventional field programmable gate array (FPGA) circuit. An FPGA is a group of logic blocks feeding a routing matrix consisting of routing lines and programmable interconnect points (PIPs). The PIPs interconnect the routing lines, and individually act as switches for selectively connecting two intersecting routing lines together. FIG. 1 illustrates only three routing lines L1-L3. In an actual chip there are many more lines, and many FPGAs, including those made by Xilinx, Inc. (assignee of the present invention) include a matrix of intersecting routing lines to which logic block input and output lines can be connected, and which can be connected to each other through PIPs. FIG. 1A illustrates one conventional structure for a PIP. Transistor T has its source and drain terminals connected to the horizontal and vertical lines which intersect at the PIP. Memory cell M applies a high or low signal to the gate of transistor T and determines whether transistor T will connect the horizontal and vertical lines. A set of configuration memory cells determine which PIPs should be on and which should be off. Memory cells are typically loaded shortly after an initialization period in which the chip is powered up, a global reset signal is asserted, and voltages throughout the chip have stabilized. Depending on the programming of each of the PIPs in the array, great routing flexibility for connecting selected logic block output lines to selected logic block input lines can be achieved.
A significant problem associated with the use of PIPs in programmable logic devices, is the contention potential which exists prior to and during device configuration. Contention occurs when PIPs simultaneously connect the outputs of two or more output drivers carrying different logic values (voltage levels) to the same node or routing line. To avoid contention before and during the configuration stage, the state of all PIPs is conventionally set to be off during and following power up. This conventional technique requires the use of a special memory cell that can power up to a known state prior to FPGA initialization. Such a memory cell is described by Hsieh in U.S. Pat. No. 4,821,233, which is incorporated herein by reference.
Contention problems also occur during reconfiguration of the FPGA. Reconfiguration is required where the FPGA is to utilize more than one programmed configuration. If configuration memory cells were sequentially switched from one configuration to another, it is likely that during the transition of the cells, both high and low voltages would simultaneously be connected to the same node. In this case, even though the reconfigured design does not cause contention, there is a likelihood that as PIPs are turned on and off to change from the first configuration to the second configuration, contention will occur.
What is needed is a circuit and method for contention free configuration and reconfiguration in a field programmable gate array.